1. Field
Exemplary embodiments of the present invention relate to a semiconductor device for eliminating a phase error between multi-phase signals using an asynchronous clock signal and an asynchronous clock signal generator for generating an asynchronous clock signal.
2. Description of the Related Art
FIG. 1A is a circuit diagram of a conventional multi-phase signal generator and FIG. 1B is a timing diagram showing its operation.
As shown in FIG. 1A, a conventional multi-phase signal generator 10 includes a plurality of variable delay circuits 11 for delaying an input clock signal Vp0 to generate a plurality of multi-phase signals, a phase comparator 20 for comparing the phase of the input clock signal Vp0 with the signal Vp5 output from the multi-phase signal generator 10, a charge pump 30 whose output voltage is adjusted by the output of the phase comparator 20, and a filter 40 for controlling the amount of delay of the multi-phase signal generator 10 in accordance with the output of the charge pump 30.
In FIG. 1A, it is preferable that two signals of adjacent phases among the multi-phase signals Vp0 to Vp4 have a phase difference that corresponds to one fifth of period of the input signal Vp0. However, as shown in FIG. 1B, the conventional multiphase signal generator compares the input signal Vp0 and the output signal Vp5, and the filter 40 stops controlling at a point where the phases of the two signals coincide with each other.
Therefore, when the amount of delay of each delay circuit 11 in the multi-phase signal generator 10 varies due to process variation or the like, the phase difference between two adjacent signals becomes uneven. That is, two adjacent signals among the multi-phase signals Vp0 to Vp4 may not have a phase difference that corresponds to one fifth of a period of the input signal Vp0.
Accordingly, a semiconductor device capable of accurately controlling the phase difference of the multi-phase signals is required.